In the transmission of digital signals from a master to a slave station (e.g. a main terminal to a remote subterminal) it is often necessary to recover the clock signal directly from the incoming data as well as provide a clock source for data being transmitted back to the main terminal. A traditional circuit for recovering the clock signal in such an application uses a resonant LC oscillator incorporating an analog phase-locked loop to synchronize it with the incoming pulse stream.
With the widescale adoption of large scale integration for digital transmission, it is desirable to implement the clock recovery circuit utilizing digital phase-locking techniques. One example of such a circuit is disclosed in U.S. Pat. No. 3,484,555, by W. K. L. Ching et al, issued Dec. 16, 1969. Here, a high-frequency clock is used to drive a frequency divider, the output of which is a recovered clock signal whose frequency is equal to the pulse repetition rate of the incoming data stream. The number of pulses from the clock is augmented in order to maintain the phase and frequency of the recovered clock in step with the received data signal. The circuit arrangement is such that even when the frequency of the recovered clock signal is exactly equal to that of the data stream, phase corrections which alternately advance or retard the phase of the signal relative to the data stream, continue to take place. In addition to this, the circuit is such that it responds to each detected transition of the input signal, the result of which is that spurious noise on the incoming data stream may be detected as a transition and cause erroneous phase shift of the recovered clock signal.